Pulse Noise Immunity in Saturated Logic Gates

This paper develops techniques for assessing the inherent pulse noise immunity of saturated logic gates, with a view towards determining their ability to operate reliably in a pulse noise environment. A test method has been outlined for specifying and measuring this noise immunity. Although this method is applicable to all forms of saturated logic, the low level T /sup 2/ L gate has been singled out for experiment because of its high speed capability. Using both discrete component and microcircuit gates of this type, close correlation was obtained between experimental results and calculations based on internal parameters of the individual devices.