| 一种带可配置插值滤波器的14-Bit 1-GS/s 数模转换器 |
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| 引用本文： | 赵琦,李冉,邱东,易婷,Bill Yang Liu,洪志良.一种带可配置插值滤波器的14-Bit 1-GS/s 数模转换器[J].半导体学报,2013,34(2):025004-8. |
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| 作者姓名： | 赵琦 李冉 邱东 易婷 Bill Yang Liu 洪志良 |
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| 作者单位： | State Key Laboratory of ASIC and System,Fudan University;Analog Devices |
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| 基金项目： | 国家高技术研究发展计划（863计划） |
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| 摘 要： | A programmable 14-bit 1-GS/s current-steering digital-to-analog converter is presented.It features a selectable interpolation rate(2x/4x/8x) with a programmable interpolation filter.To improve the high-frequency performance,a "fast switching" technique that adds additional biasing to the current-switch is adopted.The datadependent clock loading effect is also minimized with an improved switch control by using a double latch.This DAC is implemented in 65 nra CMOS technology with an active area of 1.56 mm~2.The measured SFDRs are 70.05 dB at 250 MS/s for 120.65 MHz input sine-wave signal and 64.24 dB at 960 MS/s for 56.3 MHz input sine-wave signal,respectively.
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| 关 键 词： | DAC high speed high resolution programmable |
| 收稿时间： | 6/19/2012 6:57:55 PM |
| 修稿时间： | 9/6/2012 2:34:38 PM |
A 14-bit 1-GS/s DAC with a programmable interpolation filter in 65 nm CMOS |
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| Zhao Qi,Li Ran,Qiu Dong,Yi Ting,Bill Yang Liu and Hong Zhiliang.A 14-bit 1-GS/s DAC with a programmable interpolation filter in 65 nm CMOS[J].Chinese Journal of Semiconductors,2013,34(2):025004-8. |
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| Authors: | Zhao Qi Li Ran Qiu Dong Yi Ting Bill Yang Liu and Hong Zhiliang |
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| Affiliation: | 1. State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China
2. Analog Devices, Shanghai 200021, China |
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| Abstract: | A programmable 14-bit 1-GS/s current-steering digital-to-analog converter is presented. It features a selectable interpolation rate (2x/4x/8x) with a programmable interpolation filter. To improve the high-frequency performance, a "fast switching" technique that adds additional biasing to the current-switch is adopted. The data-dependent clock loading effect is also minimized with an improved switch control by using a double latch. This DAC is implemented in 65 nm CMOS technology with an active area of 1.56 mm2. The measured SFDRs are 70.05 dB at 250 MS/s for 120.65 MHz input sine-wave signal and 64.24 dB at 960 MS/s for 56.3 MHz input sine-wave signal, respectively. |
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| Keywords: | DAC high speed high resolution programmable |
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