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| 时间校正滤波器的现场可编程门阵列实现技术 | |
| 引用本文： | 王玉峰,朱灿焰. 时间校正滤波器的现场可编程门阵列实现技术[J]. 江苏电器, 2009, 0(5): 20-24,62 |
| 作者姓名： | 王玉峰 朱灿焰 |
| 作者单位： | 苏州大学电子信息学院;苏州市科学技术情报研究所; |
| 摘 要： | 研究了用于软件无线电系统中的时间校正滤波器组的实现原理,给出了FIR滤波器分布式算法（DA）的串并行结构,分析了各种结构形式的优缺点,在此基础上提出了串并混合分布式（Mixed-DA）算法结构,给出了DA算法结构的现场可编程门阵列实现技术过程和结果。 |
| 关 键 词： | 时间校正滤波器组 分布式算法 现场可编程门阵列 |
Technology to Realize Time-Calibrating Filters in Field Programmable Gate Array |
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| WANG Yu-feng,,ZHU Can-yan. Technology to Realize Time-Calibrating Filters in Field Programmable Gate Array[J]. , 2009, 0(5): 20-24,62 | |
| Authors: | WANG Yu-feng ZHU Can-yan |
| Affiliation: | 1 School of Electronic Information;Soochow University;Suzhou 215021;China;2 Suzhou Institute of Scientific and Technical Information;Suzhou 215002;China |
| Abstract: | The principle for implementing time-calibrating filter banks, which are usually applied in software-defined systems, was studied in detail. The distributed arithmetic (DA) algorithm of FIR, its serial and pipeline implementing structures were also presented. At the same time, the advantages and disadvantages of these structures were discussed. Thus the Mixed-DA algorithm and its structure with serial and pipeline were proposed. Finally, the key techniques to realize the DA structure were shown,and some conc... |
| Keywords: | time-calibrating filter bank distributed arithmetic field programmable gate array |
| 本文献已被 CNKI 维普 等数据库收录！ | |