On-chip test circuit for measuring substrate and line-to-line coupling noise

An on-chip test circuit has been developed to directly measure substrate and line-to-line coupling noise. This test circuit has been manufactured in a 0.35 /spl mu/m double-well double polysilicon CMOS process and consists of noise generators and switched-capacitor signal processing circuitry. On-chip analog-to-digital conversion and calibration are used to eliminate off-chip noise and to extend the measurement accuracy by removing system noise. A scan circuit is described that enables the noise waveform to be reconstructed. On-chip generators ranging in area from 0.25 /spl mu/m/sup 2/ to 1.5 /spl mu/m/sup 2/ produce noise at the receiver decreasing from 3.14 mV//spl mu/m to 0.73 mV//spl mu/m. Open and closed guard rings reduce the noise by 20% and 85%, respectively. Measurement of test circuits manufactured with an epitaxial process-5.5-/spl mu/m-thick epitaxy with 20 /spl Omega//spl middot/cm resistivity on top of a 120 /spl mu/m bulk with 0.03 /spl Omega//spl middot/cm-exhibits a frequency limit of 50MHz below which coupling is insensitive to substrate noise. The difference between experimental results and an analytic model of the line-to-line coupling capacitance ranges from 8.5% to 17.7% for different metal layers.