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Relationship between power added efficiency and gate-drain avalanche in GaAs m.e.s.f.e.t.s |
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| Authors: | Wemple S.H. Steinberger M.L. Schlosser W.O. |
| Affiliation: | Bell Laboratories, Murray Hill, USA; |
| Abstract: | Pulse avalanche measurements in the transistor three-terminal configuration reveal a correlation between pulse gate-drain avalanche and power added efficiency. This result, in conjunction with earlier work, points to simple design principles that can be used to maximise efficiency. |
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