A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs |
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Authors: | Ortiz-Conde A. Garcia-Sanchez F. J. Muci J. Malobabic S. Liou J. J. |
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Affiliation: | Solid State Electron. Lab., Simon Bolivar Univ., Caracas; |
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Abstract: | In this paper, we review the compact-modeling framework for undoped double-gate (DG) silicon-on-insulator (SOI) MOSFETs. The use of multiple gates has emerged as a new technology to possibly replace the conventional planar MOSFET when its feature size is scaled to the sub-50-nm regime. MOSFET technology has been the choice for mainstream digital circuits for very large scale integration as well as for other high-frequency applications in the low-gigahertz range. But the continuing scaling of MOSFET presents many challenges, and multiple-gate, particularly DG, SOI devices seem to be attractive alternatives as they can effectively reduce the short-channel effects and yield higher current drive. Core compact models, including the analysis for surface potential and drain-current, for both the symmetric and asymmetric DG SOI MOSFETs, are discussed and compared. Numerical simulations are also included in order to assess the validity of the models reviewed |
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