指令级并行编译器的数据预取及优化方法

微处理器芯片的处理能力越来越强，但是，存储器的速度却远远不能与其匹配，造成了整个系统的性能不理想，为解决这个总理２，编译器发展了局部性优化、数据预取等多种技术，文中将介绍一种用于ＩＬＰ（Ｉｎｓｔｒｕｃｔｉｏｎ ｌｅｖ－ｅｌ Ｐａｒａｌｌｅｌｉｓｍ）优化编译器的数据预取技术以及一种利用寄存器堆减少主存访问次数、对程序进行 优化的方法，利用它们可以提高平均存储性能，对科学和工程计算的应用是相当有效的。

A Data Prefetching Method Used in ILP Compilers and Its Optimization

With the development of instruction level parallelism (ILP) technology, the processing capability of microprocessor has been increasing dramatically. Unfortunately, the speed of the whole system has not kept pace because of the imperfect speed of memory. To improve the performance of memory, locality optimization and data prefetching are developed. This paper introduces an approach of data prefetching used in ILP compiler and a method to optimize the memory system by decreasing the frequency of accessing memory. The scheme can improve the average performance of memory, especially for the science and engineering application.