| 基于FPGA的IPv6精简协议栈的设计 |
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| 引用本文： | 许川佩,郝锐.基于FPGA的IPv6精简协议栈的设计[J].计算机工程与应用,2008,44(28):113-115. |
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| 作者姓名： | 许川佩 郝锐 |
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| 作者单位： | 桂林电子科技大学 电子工程学院，广西 桂林 541004 |
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| 基金项目： | 广西省科学研究与技术开发计划项目 |
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| 摘 要： | 研究了IPv6精简协议栈的FPGA硬件实现，分析了各个模块的功能。编写了硬件结构的Verilog HDL模型，进行了仿真和逻辑综合，并成功用ALTERA的FGPA 对协议栈进行了验证。仿真和实验结果证明，所设计的硬件达到了设计要求，使小设备接入网络更加方便快捷。
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| 关 键 词： | 现场可编程门阵列 IPv6 协议栈 VerilogHDL |
| 收稿时间： | 2007-11-19 |
| 修稿时间： | 2008-2-25
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Design of reduced IPv6 stack based on FPGA |
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| XU Chuan-pei,HAO Rui.Design of reduced IPv6 stack based on FPGA[J].Computer Engineering and Applications,2008,44(28):113-115. |
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| Authors: | XU Chuan-pei HAO Rui |
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| Affiliation: | School of Electronic Engineering，Guilin University of Electronic Technology，Guilin，Guangxi 541004，China |
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| Abstract: | This paper develops a reduced IPv6 Stack based on FPGA,and analyzes the function of each module.The Verilog HDL model of the architecture is coded,simulated and synthesized.Then the design is verified by ALTERA FPGA.The results of the simulation and experiments indicate that the hardware implementation meets the design requirement,and it is more efficient for the small devices to connect to Internet. |
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| Keywords: | IPv6 Vefilog HDL |
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