Part II: A Novel Scheme to Optimize the Mixed-Signal Performance and Hot-carrier Reliability of Drain-Extended MOS Devices

The impact of scaling the depth of the shallow trench isolation (STI) region, underneath the gate-to-drain overlap, on the STI drain-extended metal–oxide–semiconductor (DeMOS) mixed-signal performance and hot-carrier behavior is systematically investigated in this work. For the first time, we discuss a dual-STI process for input/output applications. Furthermore, the differences in the hot-carrier behavior of various drain-extended devices are studied under the on- and off-states. We found that the non-STI DeMOS devices are quite prone to failure when compared with the STI DeMOS devices in both the on- and off- states. We introduced a more accurate way of predicting hot-carrier degradation in these types of devices in the on-state. We show that scaling the depth of the STI underneath the gate is the key for improving both the mixed-signal and hot-carrier reliability performances of these devices.