基于FPGA的高速采样缓存系统的设计与实现

为了提高高速数据采集系统的实时性，提出一种基于FPGA+DSP的嵌入式通用硬件结构。在该结构中，利用FPGA设计一种新型的高速采样缓存器作为高速A/D和高性能DSP之间数据通道，实现高速数据流的分流和降速。高速采样缓存器采用QuartusⅡ9.0 软件提供的软核双时钟FIFO构成乒乓操作结构，在DSP的外部存储器接口(EMIFA)接口的控制下，完成高速A/D的数据流的写入和读出。测试结果表明：在读写时钟相差较大的情况下，高速采样缓存器可以节省读取A/D采样数据时间，为DSP提供充足的信号处理时间，提高了整个系统的实时性能。

Design and implementation of high-speed sampling buffer system based on FPGA

An embedded general-purpose hardware structure based on FPGA + DSP was proposed in order to improve the real-time performance of the high-speed data acquisition system. In the structure, a new high speed sampling buffer as the data channel between the high-speed A/D and DSP was designed in FPGA and was used to realize the diversion and deceleration of high-speed data stream. The high-speed sampling buffer was based on the ping-pong operation structure of soft-core dual-clock First In First Out (FIFO) provided by Quartus Ⅱ 9.0. Under the control of the External Memory Interface A (EMIFA) interface of the DSP, it completed write-and-read operations of high-speed A/D data streams. The test results indicate that: in the case of large difference between the value of the read-and-write clock, high speed sampling buffer can save the time of the A/D sampling data to provide sufficient signal processing time for DSP, so the real-time performance of the entire system is improved. high speed sampling buffer can save the time of the A/D sampling data to provide sufficient signal processing time for DSP ,so the real-time performance of the entire system is improved.