A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process |
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| Authors: | Shirahama M Agata Y Kawasaki T Nishihara R Abe W Kuroda N Sadakata H Uchikoba T Takahashi K Egashira K Honda S Miho Miura Hashimoto S Kikukawa H Yamauchi H |
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| Affiliation: | Syst. LSI Technol. Dev. Center, Corp. Syst. LSI Dev. Div., Kyoto, Japan; |
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| Abstract: | This paper describes a standard CMOS process based on embedded DRAM macro with dual-port interleaved DRAM architecture (D/sup 2/RAM), which is suitable for the leading edge CMOS LSIs with both high-speed and large-scale memories on a chip. This macro exploits three key technologies: fully sense-signal-loss compensating technology based on the whole detailed noise element breakdowns, the novel striped trench capacitor (STC) cell, and the write-before-sensing (WBS) circuit by decoded write-bus. A 400-MHz random cycle access has been verified for D/sup 2/RAM fabricated by a 0.15-/spl mu/m standard CMOS process. |
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