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高速边界扫描主控器设计
引用本文:晏新晃,茹惠素,吴荣泉.高速边界扫描主控器设计[J].计算机工程,2009,35(1).
作者姓名:晏新晃  茹惠素  吴荣泉
作者单位:晏新晃,吴荣泉,YAN Xin-huang,WU Rong-quan(华东计算技术研究所,上海,200233);茹惠素,RU Hui-su(浙江省信息化推进服务中心,杭州,310014)  
摘    要:分析边界扫描测试技术的工作机制和对测试支撑系统的功能需求,提出一种基于USB总线的高速边界扫描测试主控器的设计方案.利用CY7C68013作为USB2.0接口控制器,使用CPLD实现JTAG主控硬核,完成JTAG协议和USB总线协议的相互转换.JTAG的TCK时钟频率可调,最高可达48 MHz.用户可利用该边界扫描控制器方便高效地进行边界扫描测试.

关 键 词:国际联合测试工作组  边界扫描  USB总线

Design of High-speed Boundary Scan Master Controller
YAN Xin-huang,RU Hui-su,WU Rong-quan.Design of High-speed Boundary Scan Master Controller[J].Computer Engineering,2009,35(1).
Authors:YAN Xin-huang  RU Hui-su  WU Rong-quan
Affiliation:1. East China Institute of Computer Technology;Shanghai 200233;2. Zhejiang Informatization Propulsion Service Centre;Hangzhou 310014
Abstract:This paper analyzes the test mechanism of boundary-scan test and the functional requirement of test supported system, and presents a design project based on USB-bus high-speed boundary scan master controller. It uses CY7C68013 as USB2.0 interface controller and uses CPLD to implement JTAG master core. So it can accomplish conversion of JTAG protocol and USB-bus protocol, and can modulate the frequency of TCK which can run at a maximum rate of 48 MHz. Users can use this boundary-scan master controller to com...
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