| 基于ACE约束的S-IRA编译码器设计 |
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| 引用本文： | 刘朋利,何欢.基于ACE约束的S-IRA编译码器设计[J].山西电子技术,2010(2):47-49,63. |
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| 作者姓名： | 刘朋利 何欢 |
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| 作者单位： | [1]解放军理工大学通信工程学院研究生3队,江苏南京210007 [2]解放军理工大学通信工程学院研究生1队,江苏南京210007 |
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| 摘 要： | 考虑到结构化非规则重复累积码具有准循环的结构便于硬件实现,采用了结构化非规则重复累积码进行编码器设计。准循环矩阵的构造采用了基于ACE约束的PEG填充构造方法。结合所用码型的特点,设计出了简单有效的编码流程图。译码方面,采用了分层修正最小和译码算法,并设计出了译码器结构。
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| 关 键 词： | 结构化非规则重复累积码 分层修正最小和译码算法 编码器结构 译码器结构 |
Design of S-IRA Code Encoder and Decoder with ACE Constrained |
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| Liu Peng-li,He Huan.Design of S-IRA Code Encoder and Decoder with ACE Constrained[J].Shanxi Electronic Technology,2010(2):47-49,63. |
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| Authors: | Liu Peng-li He Huan |
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| Affiliation: | Liu Peng-li1,He Huan2(1.Postgraduate Team 3,ICE,PLAUST,Nanjing Jiangsu 210007,China,2.Postgraduate Team 1,3.Department of Radio Communication,China) |
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| Abstract: | Motivated by the Quasi-cyclic structure and low complexity implement of hardware of S-IRA code,the encoder is designed based on it.The QC-Check matrix is designed with PEG algorithm of generalized ACE constrained.The structure of encoder is proposed concerning with the code used.A novel decoder architecture based on LMMSA decoding algorithm is also proposed and elaborated in this paper. |
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| Keywords: | S-IRA code LMMSA algorithm encoder architecture decoder architecture |
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