22 nm FDSOI工艺SRAM单粒子效应的重离子实验研究

针对22 nm全耗尽绝缘体上硅（FDSOI）工艺静态随机存储器（SRAM）开展了重离子实验，对比了不同加固设计的FDSOI SRAM的抗单粒子翻转（SEU）和多单元翻转（MCU）能力，分析了读写错误致存储阵列MCU的效应表征和作用机制，揭示了衬底偏置对FDSOI SRAM SEU敏感性的影响机理。研究结果表明：对5款被测FDSOI SRAM而言，抗SEU能力由弱到强依次为八管加固型SRAM2、冗余加固型SRAM1、双互锁结构（DICE）型SRAM3或SRAM4、双DICE型SRAM5；3款DICE型FDSOI SRAM的存储阵列自身抗MCU性能优于其他两款SRAM；虽然DICE型FDSOI SRAM的存储阵列自身抗MCU能力强，但读写错误致存储阵列MCU的影响不可忽略，且该影响随SRAM工作频率的提高愈加严重；衬底偏置通过对寄生双极放大效应的控制来影响FDSOI SRAM的SEU敏感性。

Heavy Ion Experiment Research of Single Event Effect in 22 nm FDSOI Technology SRAM

The heavy ion experiment was carried out for the static random array memory (SRAM) fabricated with the 22 nm fully depleted silicon on insulator (FDSOI) technology. The single event upset (SEU) and multiple cell upset (MCU) sensitivities of FDSOI SRAM with different radiation hardened designs were compared. The characterization and mechanism of MCU induced by read write errors were analyzed. The influence of the substrate bias voltage on FDSOI SRAM SEU sensitivity was revealed. The results show that for five investigated FDSOI SRAMs, the anti SEU capability is from weak to strong in order of 8 T SRAM2, redundancy designed SRAM1, dual interlocked cell (DICE) SRAM3 or SRAM4, and dual DICE SRAM5. The memory arrays of the three DICE type FDSOI SRAMs have better anti MCU performance than those of the other two SRAMs. Although the memory arrays of DICE type FDSOI SRAMs had strong anti MCU capability, the influence of read write errors inducing MCU on DICE type FDSOI SRAMs could not be ignored, and the influence is found to be more serious with the increase of SRAM operation frequency. The substrate bias voltage affects the FDSOI SRAMs upset sensitivity by controlling the parasitic bipolar amplification effect.