Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes |
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| Affiliation: | 1. Finnish Meteorological Institute, Atmospheric Composition Research, Erik Palménin aukio 1, FIN-00560 Helsinki, Finland;2. Alfred-Wegener-Institut Helmholtz-Zentrum für Polar- und Meeresforschung, Am Handelshafen 12, 27570 Bremenhaven, Germany;1. Department of Electrical Engineering, Tshwane University of Technology Private Bag X680, Pretoria 0001, RSA;2. Laboratoire d’Electrotechnique et d’Electronique de Puissance de Lille, université Lille1 IRCICA, 50 Avenue Halley, 59650 Villeneuve d’Ascq France;1. University of Groningen, Nijenborgh 4, NL-9747 AG Groningen, The Netherlands;2. Institute for Theoretical Physics, Universität Tübingen, Auf der Morgenstelle 14, D-72076 Tübingen, Germany |
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| Abstract: | This paper approaches the memory bottleneck problem in FPGA-accelerated codes processing unstructured meshes. A methodology to reduce the required memory bandwidth is presented and evaluated, based on the combined application of data sorting, coding and compression techniques. Sorting allows efficient streaming between the memory and the FPGA, improving data locality and avoiding redundant data requests. Coding achieves a compact representation of the mesh connectivity. Differential compression reduces the size of the mesh data. We propose a hardware implementation with low resource requirements, tailored to accelerators based on reconfigurable devices. The combination of techniques reduces the memory traffic of two computational problems down to an average 34% and 19% of their original sizes, respectively. |
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| Keywords: | Memory FPGA Sorting Coding Compression Unstructured mesh |
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