一种高性能硬件加密引擎阵列架构

该文提出一种高性能硬件加密引擎阵列架构，为大数据应用提供了先进的安全解决方案。该模块架构包括一个高速接口、一个中央管理和监视模块(CMMM)、一组多通道驱动加密引擎阵列，其中CMMM将任务分配给加密引擎，经由专用算法处理后再将数据传回主机。由于接口吞吐量和加密引擎阵列规模会限制模块性能，针对PCIe高速接口，采用MMC/eMMC总线连接构建阵列，发现更多加密引擎集成到系统后，模块性能将会得到提升。为验证该架构，使用55 nm制程工艺完成了一个PCIe Gen2×4接口的ASIC加密卡，测试结果显示其平均吞吐量高达419.23 MB。

High Performance Crypto Module with Array of Hardware Engines

A high-performance crypto module prescribed in this paper offers advanced security solutions in big data applications. A module architecture, which consists of a high throughput interface, Central Manage & Monitor Module (CMMM) and multiple channels driving a group of crypto engines, is discussed here. CMMM distributes the tasks to the crypto engines and guides the data back to the host after processing by the dedicated algorithm. Since the module's performance is limited by the interface throughput and the scale of the crypto engines, an array with MMC/eMMC bus connections is built for PCIe high-speed interfaces. The more crypto engines are integrated into a system, the higher performance of this system can reach. To verify this architecture, an ASIC encryption card with PCIe Gen2×4 interface is made under semiconductor manufacturing process technology of 55 nm, and tested. The average throughput of this card can achieve up to 419.23 MB.