Comments on “New dynamic flip-flops for high-speeddual-modulus prescaler”

For the original paper see ibid., vol. 33, no. 10, p. 1568-1571 (1998). In the aforementioned paper a fast true single-phase clocking (TSPC) ratioed D-flip-flop is proposed by C. Yang et al. It is claimed by the commenters that the proposed flip-flop violates the edge-triggering characteristic. However, it is shown that high clock frequency and the propagation delay of the transistor enable the flip-flop to operate normally in the dual-modulus prescaler