| 可重构Viterbi基核单元的设计与实现 |
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| 引用本文： | 尹蕾,李广军.可重构Viterbi基核单元的设计与实现[J].微电子学,2007,37(5):674-677. |
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| 作者姓名： | 尹蕾 李广军 |
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| 作者单位： | 电子科技大学,通信与信息工程学院,成都,610054 |
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| 摘 要： | 为适应多种通信标准,提出了一种新的可重构Viterbi译码器基核单元,由该基核单元可动态重构成不同约束长度(3~9)、不同编码效率(1/2或1/3)以及不同生成多项式的Viterbi译码器。在Xilinx Virtex4系列FPGA上,对该基核单元组成的译码器进行综合实现,并进行了仿真。结果表明,该译码器的速度能达到50 Mbps,适合在802.11无线局域网及3G网络中使用。
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| 关 键 词： | 可重构 基核单元 |
| 文章编号： | 1004-3365（2007）05-0674-04 |
| 修稿时间： | 2007-05-09 |
Design and Implementation of Reconfigurable Viterbi Fabric |
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| YIN Lei,LI Guang-jun.Design and Implementation of Reconfigurable Viterbi Fabric[J].Microelectronics,2007,37(5):674-677. |
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| Authors: | YIN Lei LI Guang-jun |
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| Affiliation: | Inst, of Commun. and In for. Engineer., Univ. ofElec, Sci, and Technol. of China, Chengdu 610054, P, R. China |
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| Abstract: | A new reconfigurable Viterbi fabric was proposed to adapt to multi-standard.Using this fabric,Viterbi decoder with different constraint lengths,different code rates and different generation polynomials can be composed.The decoder was implemented in Xilinx Virtex4 FPGA.Simulation results show that the proposed decoder has a throughput of 40 Mbps,and it is applicable for receiver architecture in 802.11a wireless LAN and 3G environment. |
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| Keywords: | Viterbi FPGA |
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