An IEEE 1149.1 Compliant Test Control Architecture |
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Authors: | Debaditya Mukherjee Melvin A Breuer |
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Affiliation: | (1) Santa Clara Processor Division, Intel Corporation, Santa Clara, CA, 95052-8119;(2) Department of Electrical Engineering-Systems, University of Southern California, University Park, Los Angeles, CA, 90089-2562 |
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Abstract: | This paper deals with a design methodology and associated architecture to support the control of on-chip DFT and BIST hardware. The work is general in that it supports numerous test methods, such as partial and full scan, multiple and reconfigurable scan chains, and both test per clock BIST and scan BIST. The results presented here are compatible with the IEEE 1149.1 boundary scan architecture. The work is based on a hierarchical control methodology that includes systems, PCBs and MCMs. Various options for assigning control functions to be on-chip or off-chip are described. A new, partially distributed test control architecture is introduced that includes an internal test bus and distributed local controllers. There are three main modes of control of test resources, namely local static control, dynamic control and global static control. We show how the control mechanism can be implemented together with the IEEE 1149.1 test protocol. The synthesis of the on-chip test control hardware has been automated in a system called CONSYST. |
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Keywords: | test control boundary scan built-in self-test design-for-test test bus local test control distributed test control dynamic test control |
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