Harris算法硬件加速设计

针对序列图像实时边缘和角点检测应用需求,对Harris算法进行了硬件加速设计,提出了一种内嵌并行运算的流水线结构。采取分解简化高斯模板、流水实现复杂计算、缓存灰度数据并并行计算一阶差分及其乘积等措施提高算法的实时处理能力,减少硬件资源消耗。ModeISim仿真结果和ISE综合报告显示,与常规方法相比,该设计在性能、速度和硬件资源消耗方面均表现较好,在实时图像处理应用领域有较好的实用价值。

Hardware-accelerated design for Harris algorithm

Aiming at the application requirements of real-time corner detection in image sequences,hardware-accelerated design is done for Harris corner detection,and pipeline architecture with internal parallel operation is proposed.Several measures such as decomposing and simplifying Gaussian model,implementing complex computation in pipeline,storing intensity data as well as computing the first derivatives and their products in parallel are taken to improve the real-time performance and reduce hardware resources consumption.The results of ModelSim simulation and the synthesis report of ISE indicate that the proposed design performs better than regular methods in performance,speed and hardware resources cost,and it is valuable in real-time image processing.