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Performance Analysis of Gate-Stack Dual-Material DG MOSFET Using Work-Function Modulation Technique for Lower Technology Nodes |
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| Authors: | Das Satish K Nanda Umakanta Biswal Sudhansu M Pandey Chandan Kumar Giri Lalat Indu |
| Affiliation: | 1.Department of Electronics and Communication Engineering, Silicon Institute of Technology, Bhubaneswar, Odisha, India ;2.School of Electronics Engineering, VIT-AP University, Inavolu, Beside AP Secretariat, Near Vijayawada, Andhra Pradesh, India ;3.Department of Electronics and Instrumentation Engineering, Silicon Institute of Technology, Bhubaneswar, Odisha, India ;4.Department of Electronics and Communication Engineering, NIT, Goa, Ponda, Goa, India ; |
| Abstract: | Silicon - Short channel effects (SCEs) along with mobility degradation has a great impact on CMOS technology below 100 nm. These effects can be overcome by using gate and channel... |
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