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Assessment of Interface Trap Charges on Proposed TFET for Low Power High-Frequency Application |
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| Authors: | Kumar Sachin Yadav Dharmendra Singh |
| Affiliation: | 1.National Institute of Technology Hamirpur, Himachal Pradesh, 177005, India ; |
| Abstract: | Silicon - Accumulation of trap charges at the semiconductor and oxide interface is the most dominating factor and cannot be neglected as it degrades device performance and reliability. This... |
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