纳米电路交叉冗余容错技术研究 |
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引用本文: | 张洋,王友仁,张砦.纳米电路交叉冗余容错技术研究[J].佳木斯工学院学报,2010(1):5-8. |
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作者姓名: | 张洋 王友仁 张砦 |
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作者单位: | 南京航空航天大学自动化学院,江苏南京210016 |
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摘 要: | 提出了一种针对纳米电路的数字电路容错设计新方法.该方法基于交叉冗余原理,利用两种二进制错误的不对称性,采用模块化方法对纳米电路进行容错设计.以阵列乘法器为例,采用新方法对电路进行设计和仿真,并结合实验结果与传统的可重构和三模冗余容错方法进行比较.交叉冗余方法无需检测模块及表决器,不会增加系统延时,并且在资源消耗方面远低于传统方法,对纳米电路尤其适用.
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关 键 词: | 纳米电路 容错 交叉冗余 可靠性 故障屏蔽 |
Research on Fault - tolerant Techniques Based on Interwoven Redundancy for Nanoscale Circuits |
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Authors: | ZHANG Yang WANG You- ren ZHANG Zhai |
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Affiliation: | (College of Antomation and Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, 210016, China) |
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Abstract: | A new method for designing fault - tolerant digital circuits to reduce the failure rate of nanoscale circuits based on interwoven redundancy and the asymmetric of two kinds of binary errors, using a modular approach to design circuits. With multiplier as an example, this paper conducted a simulation experiment using the new method. The results show that it is better than the traditional fault - tolerant design methods. The new method is especially suitable for nano - circuits because it won' t increase the system delay without detection module and voter, and its resource consumption is far less than that of traditional methods. |
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Keywords: | nano - circuits fault - tolerant interwoven redundant reliability fault masking |
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