| 2.5 Gbps收发器中1∶2解复用电路的设计 |
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| 引用本文： | 邓军勇,蒋林,曾泽沧.2.5 Gbps收发器中1∶2解复用电路的设计[J].电子设计工程,2014(9):101-103. |
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| 作者姓名： | 邓军勇 蒋林 曾泽沧 |
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| 作者单位： | 西安邮电大学电子工程学院,陕西西安710121 |
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| 基金项目： | 国家自然科学基金项目（61272120）;陕西省教育厅专项科研计划项目（2010JK817） |
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| 摘 要： | 在2.5 Gbps高速串行收发系统接收端中1到2解复用电路位对于降低内核工作速度,减轻设计压力,提高电路稳定性起着关键作用.本文描述了基于电流模式逻辑的解复用电路工作原理,按照全定制设计流程采用SMIC0.18um混合信号工艺完成了高速差分数据的1到2解复用,并采用SpectreVerilog进行了数模混合仿真,结果表明该电路在2.5 Gbps收发器电路中可以稳定可靠地工作.
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| 关 键 词： | 解复用电路 电流模式逻辑 混合仿真 半速率结构 |
Design of 1∶2 demultiplexer circuit in 2.5Gbps transceiver |
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| DENG Jun-yong,JIANG Lin,ZENG Ze-cang.Design of 1∶2 demultiplexer circuit in 2.5Gbps transceiver[J].Electronic Design Engineering,2014(9):101-103. |
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| Authors: | DENG Jun-yong JIANG Lin ZENG Ze-cang |
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| Affiliation: | (School of Electronic Engineering, Xi＇an University of Posts ＆ Telecommunications, Xi＇an 710121,China) |
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| Abstract: | The 1 to 2 demultiplexer plays a key role in 2.5Gbps serial transceiver for decreasing the core speed,easing design challenge,and improving the circuit stability.This paper analyzes the operating principle of demultiplexer based on current mode logic,accomplishes the 1 to 2 demultiplexing for high speed differential data with SMIC 0.18um mixed-signal process under full-custom design.The proposed circuit is simulated with SpectraVerilog,and the results show that the circuit can work stably in the 2.5Gbps transeceiver. |
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| Keywords: | demultiplexer current mode logic mixed-simulation half-speed architecture |
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