Dynamic architectures for microcomputers

This paper describes low cost dynamic architectures for microcomputers. The proposed architectures allow the CPU to be simultaneously active during DMA block I/O operations. As a result, a considerable speed advantage may be obtained at very little extra cost. An experimental system has been built and successfully tested. Several computational environments have been simulated on the prototype system. Some alternative designs with varying degrees of flexibility and hardware cost are discussed. The designs are aimed primarily at total overlap of I/O interfaces and processor activities. Emulation data show that in many application environments the proposed architectures could provide substantially higher throughputs than conventional static architectures.