基于全耗尽技术的SOI CMOS集成电路研究

介绍了电路的工作原理，对主要的延迟和选通控制单元及整体电路进行了模拟仿真，证明电路逻辑功能达到设计要求。根据电路的性能特点，采用绝缘体上硅结构，选用薄膜全耗尽SOICMOS工艺进行试制。测试结果表明：与同类体硅电路相比，工作频率提高三倍，静态功耗仅为体硅电路的10％，且电路的101级环振总延迟时问也仅为体硅电路的20％，实现了电路对高速低功耗的要求。

Research of SOI CMOS Integrated Circuit Based on Fully Depleted Technology

A functional block diagram of a novel and high-performance fully-depleted SOI CMOS for pulse measurement circuit was introduced. Delay element, strobe control element, and fully-depleted SOI CMOS for pulse measurement device were simulated. The logical function of the circuit met the needs of the design were checked by simulation oscillogram. The structure of the silicon-on-insulator was adopted on the basic of the circuit character. The technology of fully-depleted SOI CMOS with thin silicon film was selected, and the device was fabricated. Based on the simulation, optimization and fabrication of the circuit, a well-behaved characteristics were achieved. The test results show that the operating frequency of the 1.9, micron SOI CMOS circuit is 3 times than that of the bulk silicon circuit. The static power dissipation is only 10 percent and the propagation delay per-stage of 101-stage ring oscillators is 20 percent of the bulk silicon ones. A device with highspeed and low-power dissipation was achieved.