Carrier Modulation in 2D Transistors by Inserting Interfacial Dielectric Layer for Area-Efficient Computation |
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Authors: | Zheng Bian Jialei Miao Tianjiao Zhang Haohan Chen Qinghai Zhu Jian Chai Feng Tian Shaoxiong Wu Yang Xu Bin Yu Yang Chai Yuda Zhao |
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Affiliation: | 1. School of Micro-Nano Electronics, Hangzhou Global Scientific and Technological Innovation Centre, Zhejiang University, 38 Zheda Road, Hangzhou, 310027 China;2. Department of Applied Physics, The Hong Kong Polytechnic University, Hong Kong, 999077 China |
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Abstract: | 2D materials with atomic thickness display strong gate controllability and emerge as promising materials to build area-efficient electronic circuits. However, achieving the effective and nondestructive modulation of carrier density/type in 2D materials is still challenging because the introduction of dopants will greatly degrade the carrier transport via Coulomb scattering. Here, a strategy to control the polarity of tungsten diselenide (WSe2) field-effect transistors (FETs) via introducing hexagonal boron nitride (h-BN) as the interfacial dielectric layer is devised. By modulating the h-BN thickness, the carrier type of WSe2 FETs has been switched from hole to electron. The ultrathin body of WSe2, combined with the effective polarity control, together contribute to the versatile single-transistor logic gates, including NOR, AND, and XNOR gates, and the operation of only two transistors as a half adder in logic circuits. Compared with the use of 12 transistors based on static Si CMOS technology, the transistor number of the half adder is reduced by 83.3%. The unique carrier modulation approach has general applicability toward 2D logic gates and circuits for the improvement of area efficiency in logic computation. |
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Keywords: | 2D materials carrier modulation double-gate transistors logic gates WSe
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