一种CMP结构上的事务存储编程模型设计

多核结构上采用由用户显式制导的并行程序设计模型,使用锁和同步变量来实现同步.事务存储模型能够解决由锁机制带来的一系列问题,提高程序的并发性.介绍了在文中提出的一种基于事务存储模型的多核结构(Transactional-Memory based Chip Multiple-Superscaler,TMCMS)上的并行编程模型,以及针对循环程序的执行模型;以FFT程序为例具体介绍了循环结构的并行化方法和编译转换过程.在初步的实验中,将处理单元从1增加到16个时,在所设计的编程模型的支持下,IPC(Instruction Per Cycle)有接近线性的增长,说明该并行编程模型能够充分发掘程序中潜在的细粒度线程级并行性,同时保持并行程序设计的简单性.

A Programming Model for Chip Multi-Processor Based on Transactional Memory

Traditional parallel programming models have many limitations when applied to multi-core, or programmers have to explicitly identify synchronization on Multiprocessor with locks and synchronous variables. Transactional Memory can solve problems brought by locks and improve parallelism. This paper introduces a programming model on TMCMS (Transactional-Memory based Chip Multiple-Superscaler) which is a CMP architecture based on Transactional-Memory model, and its execution model for loop-based program. FFT program is used as an example to illustrate the method of loop structure paralleling and to describe compiler-directed translation in detail. The performance of the model is evaluated by varying the processor unit size from 1 to 16, and the IPC (instruction per cycle) increases nearly linearly with the number of processor unit. The preliminary experiment results indicate that this programming model can sufficiently exploit fine-grained parallelism in the program while maintaining the simplicity of parallel programming.