| 32位无符号并行乘法器的设计与实现 |
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| 引用本文： | 胡小龙,颜煦阳. 32位无符号并行乘法器的设计与实现[J]. 计算机工程与科学, 2010, 32(4): 122-124. DOI: 10.3969/j.issn.1007130X.2010. |
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| 作者姓名： | 胡小龙 颜煦阳 |
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| 作者单位： | 中南大学信息科学与工程学院,湖南,长沙,410075;中南大学信息科学与工程学院,湖南,长沙,410075 |
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| 摘 要： | 在基4的Booth算法得到部分积的基础上,采用了优化后的4:2压缩器的Wallace树对部分积求和,最后用CPA得到最终的和。优化下的并行乘法器比传统的CSA阵列乘法器速度快,且延时小。用Verilog进行了功能描述,并用ISE9.2对其进行了综合。
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| 关 键 词： | 并行乘法器 Booth算法 4:2压缩器 Wallace树 |
| 收稿时间： | 2008-11-21 |
| 修稿时间： | 2009-02-08 |
Design and Implementation of a 32-Bit Unsigned Parallel Multiplier |
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| HU Xiao-long,YAN Xu-yang. Design and Implementation of a 32-Bit Unsigned Parallel Multiplier[J]. Computer Engineering & Science, 2010, 32(4): 122-124. DOI: 10.3969/j.issn.1007130X.2010. |
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| Authors: | HU Xiao-long YAN Xu-yang |
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| Affiliation: | School of Information Science and Engineering/a>;Central South University/a>;Changsha 410075/a>;China |
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| Abstract: | Based on the traditional Booth 4 algorithm,we adopt the Wallace tree of a balanced 4:2 compressor to compute the sum of partial products and finally use CPA to get the final sum. It is shown that this scheme has a higher speed and a small delay than the traditional CSA array multiplier.The circuit is described using the Verilog HDL language and is synthesized by ISE9.2. |
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| Keywords: | parallel multiplier Booth algorithm 4:2 compressor Wallace tree |
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