| SoC芯片中关键路径的优化方法研究 |
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| 引用本文： | 李黎,付宇卓,汪宁. SoC芯片中关键路径的优化方法研究[J]. 微电子学与计算机, 2006, 23(4): 141-145 |
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| 作者姓名： | 李黎 付宇卓 汪宁 |
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| 作者单位： | 上海交通大学微电子学院,上海,200030 |
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| 摘 要： | 文章对Soc系统综合时关键路径的处理方法进行了研究，从多路器电路、状态机电路以及算术单元电路三个角度，分析各种实现方式的利弊，提出了在满足系统性能的要求下进行代码设计优化的指导原则和方法，并且用Design Compiler进行综合并分析其结果。
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| 关 键 词： | 综合 RTL优化 关键路径 |
| 文章编号： | 1000-7180（2006）04-141-05 |
| 收稿时间： | 2005-07-28 |
| 修稿时间： | 2005-07-28 |
The Optimization of Critical Path in Synthesis of SoC |
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| LI Li,FU Yu-zhuo,WANG Ning. The Optimization of Critical Path in Synthesis of SoC[J]. Microelectronics & Computer, 2006, 23(4): 141-145 |
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| Authors: | LI Li FU Yu-zhuo WANG Ning |
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| Affiliation: | School of Microelectronics, Shanghai Jiaotong University, Shanghai 200030 |
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| Abstract: | This paper studies the optimization of the critical path in SoC synthesis. The author presents different implementation methods for multiplexer circuit, state machine circuit and arithmetic logic unit circuit, analyzes the benefits and shortages and discusses how to optimize the RTL design to meet the performance requirement of the system, The timing and area results are also analyzed by Design Compiler. |
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| Keywords: | SoC |
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