一种低消耗高效能的AES加密算法芯片设计

在一些便携式电子设备中,希望使用小面积、低功耗的加密芯片。首先介绍AES加密算法,结合该算法的变换特点,为了降低AES硬件实现的面积和功耗,引入CSE(Common Subex-pression Elimination)算法对其关键模块进行优化;设计了仅仅使用4个sbox和一列mixcolumn的系统结构,结构中又将加密和解密进行了有机的结合。结果表明,该设计方案有效地减小了其硬件实现时的开销。

A Low-cost and Effective VLSI Design of AES

In many portal electronic devices,we hope use the small area and low energy-consuming encryption chip.At first,introducing the AES algorithm,then combining with the characterization of AES algorithm transformation,we use the CSE(Common Sub-expression Elimination) to optimize the main modules of AES for reducing the hardware area and energy-consume of AES chip;In our design,the architecture of AES with the 4-Sboxes and one-column Mix-Column was used,this architecture also integrated the Encryption and Decryption functions.The result shows that our design of AES reduced the hardware-cost effectively.