Simulation study of Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for high temperature applications |
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| Authors: | Vandana Kumari Manoj Saxena R.S. Gupta Mridula Gupta |
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| Affiliation: | 1. Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi, South Campus, New Delhi 110 021, India;2. Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, New Delhi, India;3. Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology, New Delhi, India |
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| Abstract: | This paper analyzes the effect of temperature variation on various device architectures i.e. Insulated Shallow Extension Silicon On Nothing (ISESON), ISE and SON MOSFET using ATLAS 3D device simulator for 45 nm gate length. The simulation results obtained with the ATLAS has been validated by comparing it with reported experimental data of SON MOSFET. The simulation results demonstrate that out of three device designs, the ISESON MOSFET is the most suitable device for high speed, low voltage and high temperature applications. The integration of ISE and SON onto the conventional bulk MOSFET leads to the enhancement in analog device performance in terms of device efficiency (gm/Ids), device gain (gm/gd), output resistance (Rout) and early voltage (Vea). |
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