重用感知的非一致缓存迁移策略研究

随着工艺的持续进步,多核处理器集成了越来越多的核以及片上缓存系统,因此利用非一致缓存架构(NUCA)应对片上多核处理器的缓存系统中逐渐增大的线延迟。高效的缓存块迁移策略对整个缓存系统至关重要。当前动态非一致缓存架构(D-NUCA)中的缓存块迁移策略未考虑缓存块的历史访问信息,导致缓存块在不同的bank之间抖动从而增加缓存块的访问延迟。为此,提出一种重用感知的缓存块迁移(RABM)策略,采用缓存块的历史迁移信息来预测将来的缓存块迁移,从而提升D-NUCA的性能以及降低整个缓存系统的功耗。基于PARSEC基准测试程序的全系统仿真结果显示,与D-NUCA相比,基于RABM的D-NUCA可以使每时钟周期指令数平均提高9.6%,片上缓存系统功耗降低14%。

Research on Reuse-aware Non-uniform Cache Migration Strategy

As technology scales down, more and more cores are integrated into single chip with larger and larger cache memories. Recently, Non-uniform Cache Architecture（NUCA） is proposed to mitigate the increasing wire delay for cache memories in multi-core systems. High performance block migration policy is crucial for the overall performance of the memory subsystem in multi-core systems. The block access information is not considered in the design of block migration strategy of Dynamic NUCA（D-NUCA） which can lead to the jitter of blocks among different cache banks, result in even longer access latency. Aiming at the lack of efficient block migration strategy, this paper proposes a Reuse-aware Block Migration（RABM） for D-NUCA. Through exploiting the historical block migration information as the hint, the proposed migration strategy can effectively improve the performance of D-NUCA and reduce caching system power consumption. Full system simulation result based on PARSEC benchmark test program show that D-NUCA based on RABM improves the Instruction per Cycle（IPC） by 9.6% on average, and reduces on-chip cache system power consumption by 14% on average compared with D-NUCA.