| 基于FPGA的单精度浮点数乘法器设计 |
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| 引用本文： | 旷捷,毛雪莹,彭俊淇,黄启俊,常胜.基于FPGA的单精度浮点数乘法器设计[J].电子技术应用,2010,36(5). |
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| 作者姓名： | 旷捷 毛雪莹 彭俊淇 黄启俊 常胜 |
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| 作者单位： | 武汉大学,物理科学与技术学院,湖北,武汉,430072 |
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| 摘 要： | 设计了一个基于FPGA的单精度浮点数乘法器。设计中采用改进的带偏移量的冗余Booth3算法和跳跃式Wallace树型结构,并提出对Wallace树产生的2个伪和采用部分相加的方式,提高了乘法器的运算速度;加入对特殊值的处理模块,完善了乘法器的功能。本设计在AlteraDE2开发板上进行了验证。
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| 关 键 词： | 改进的带偏移量的冗余Booth3算法 跳跃式Wallace树 单精度浮点数乘法器 FPGA |
An FPGA implementation of single precision floating-point multiplier |
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| KUANG Jie,MAO Xue Ying,PENG Jun Qi,HUANG Qi Jun,CHANG Sheng.An FPGA implementation of single precision floating-point multiplier[J].Application of Electronic Technique,2010,36(5). |
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| Authors: | KUANG Jie MAO Xue Ying PENG Jun Qi HUANG Qi Jun CHANG Sheng |
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| Affiliation: | KUANG Jie,MAO Xue Ying,PENG Jun Qi,HUANG Qi Jun,CHANG Sheng (Department of Physics Science and Technology,Wuhan University,Wuhan 430072,China) |
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| Abstract: | An FPGA implementation of single precision floating-point multiplier is introduced in this thesis. With the usage of modified redundant Booth3 with bias and leapfrog Wallace tree, and the application of partial addition in fixed-point multiplication, the efficiency of the 5 -stage multiplier is promoted. Moreover, a module dealing with special values is introduced to perfect the function of the multiplier. The verification of the multiplier is accomplished on Altera DE2. |
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| Keywords: | FPGA |
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