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Graceful degradation for reducing jitter of battery life in fault-tolerant embedded systems
Authors:Salim Kalla  Riadh Hocine  Abderrezak Chouki
Affiliation:1. LaSTIC Laboratory, Department of Computer Science, University of Batna 2, Batna, Algeria;2. Department of Computer Science, University of Hadj Lakhdar Batna, Batna, Algeria
Abstract:Tolerating faults and minimising energy consumption in embedded systems is a difficult task due to the fact that the two objectives are antagonistic. In this paper, we propose a new approach based on graceful degradation to reduce jitter of battery life and thereby energy consumption in fault-tolerant embedded systems. In case of faults, the affected task is re-executed. In our solution, the energy level of battery is periodically verified, and if we detect that the continuity with the current operating mode leads to jitter, the system gracefully degrades to the adequate operating mode. In such degraded mode, the dynamic voltage scaling technique is used to save energy. The effectiveness of using graceful degradation is depending on the application criticality level. Simulation results show that the use of graceful degradation can reduce jitter of battery life, and thereby can minimise energy consumption.
Keywords:Embedded systems  real-time systems  energy management  fault tolerance  graceful degradation  dynamic voltage scaling
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