新型的3D堆叠封装制备工艺及其实验测试

为了满足超大规模集成电路(VLSI)芯片高性能、多功能、小尺寸和低功耗的需求,采用了一种基于贯穿硅通孔(TSV)技术的3D堆叠式封装模型.先用深反应离子刻蚀法(DRIE)形成通孔,然后利用离子化金属电浆(IMP)溅镀法填充通孔,最后用Cu/Sn混合凸点互连芯片和基板,从而形成了3D堆叠式封装的制备工艺样本.对该样本的接触电阻进行了实验测试,结果表明,100 μm2Cu/Sn混合凸点接触电阻约为6.7 mΩ高90 μm的斜通孔电阻在20～30mΩ该模型在高达10 GHz的频率下具有良好的机械和电气性能.

Fabrication and Test of Novel 3D Stacked Packages

To meet more high-performance,more features,smaller size and lower power requirements in chips of VLSI,3D stacked packages process model based on through silicon vias were adopted.Via holes were formed by deep reactive ion etching(DRIE),then the via holes were filled by ionized metal plasma(IMP)sputtering method,at last Cu/Sn bump was used for chip-to-substrate bonding to form the fabrication sample.Through the experiments of contact resistances,testing shows that the contact resistance of Cu/Sn bump joints...