Conventional and machine learning approaches as countermeasures against hardware trojan attacks |
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| Affiliation: | 1. CAS-lab Group, Department of Electrical and Computer Engineering, School of Engineering, University of Thessaly, Volos, Hellas;2. AIDEAS, Tallinn, Estonia;3. Department of Computer Engineering & Informatics, University of Patras, Patra, Hellas;1. Department of Electrical and Electronics Engineering, R.M.K. College of Engineering and Technology, Thiruvallur, Tamil Nadu, India;2. Department of Electrical and Electronics Engineering, R.M.K. Engineering College, Thiruvallur, Tamil Nadu, India;1. Associate Professor, Department of Electronics and Communication Engineering, Excel college of Engineering and Technology, Komarapalayam, Tamilnadu, India;2. Associate professor, Department of Electrical and Electronics Engineering, Sona College of Technology, Salem, Tamilnadu, India;1. Research Scholar, Department of Electronics & Communication Engineering, SRM Institute of Science and Technology, Chennai, India;2. Associate Professor, Department of Electronics & Communication Engineering, SRM Institute of Science and Technology, Chennai, India;3. Assistant Professor, Department of Telecommunication Engineering, SRM Institute of Science and Technology, Chennai, India |
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| Abstract: | Every year, the rate at which technology is applied on areas of our everyday life is increasing at a steady pace. This rapid development drives the technology companies to design and fabricate their integrated circuits (ICs) in non-trustworthy outsourcing foundries to reduce the cost, thus, leaving space for a synchronous form of virus, known as Hardware Trojan (HT), to be developed. HTs leak encrypted information, degrade device performance or lead to total destruction. To reduce the risks associated with these viruses, various approaches have been developed aiming to prevent and detect them, based on conventional or machine learning methods. Ideally, any undesired modification made to an IC should be detectable by pre-silicon verification/simulation and post-silicon testing. The infected circuit can be inserted in different stages of the manufacturing process, rendering the detection of HTs a complicated procedure. In this paper, we present a comprehensive review of research dedicated to countermeasures against HTs embedded into ICs. The literature is grouped in four main categories; (a) conventional HT detection approaches, (b) machine learning for HT countermeasures, (c) design for security and (d) runtime monitor. |
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