| 用边界元法提取VLSI版图电阻 |
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| 引用本文： | 胡庆生,汪晓岩.用边界元法提取VLSI版图电阻[J].微电子学,1996,26(6):363-367. |
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| 作者姓名： | 胡庆生 汪晓岩 |
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| 作者单位： | [1]上海交通大学大规模集成电路研究所 [2]电子工业部第38研究所 |
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| 摘 要： | 介绍了ＶＬＳＩ版图验证中电阻提取的基本原理和主要方法，给出了一种新颖的基于边界元法的电阻提取算法。该算法采用变节点单元，较好地解决了实际问题中经常出现的角点问题。通过应用该算法对几个实例进行提取，证明使用本文的算法不仅在精度上而且在占用ＣＰＵ时间上都取得了令人满意的效果
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| 关 键 词： | VLSI IC CAD 版图验证 电阻提取 边界元法 |
A VLSI Resistance Extractor Using Boundary Element Method |
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| HU Qingsheng,LIN Zhenghui LSI Institute,Shanghai Jiaotong University,Shanghai WANG Xiaoyan East China Research Institute of Electronic Engineering,Hefei,Anhui.A VLSI Resistance Extractor Using Boundary Element Method[J].Microelectronics,1996,26(6):363-367. |
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| Authors: | HU Qingsheng LIN Zhenghui LSI Institute Shanghai Jiaotong University Shanghai WANG Xiaoyan East China Research Institute of Electronic Engineering Hefei Anhui |
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| Affiliation: | HU Qingsheng,LIN Zhenghui LSI Institute,Shanghai Jiaotong University,Shanghai 200030 WANG Xiaoyan East China Research Institute of Electronic Engineering,Hefei,Anhui 230031 |
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| Abstract: | The basic theory of resistance extraction in VLSI layout verification is described.A novel resistance extractor based on the boundary element method is presented.In this technique,the corner node problems commonly encountered in practice is solved by using the changeable elements.Actual processing of some examples demonstrates that not only can the proposed algorithm meet the requirement for accuracy,but it is effective in CPU time. |
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| Keywords: | VLSI IC CAD Layout verification Resistance extraction Boundary element method EEACC 2120 2570A |
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