一种高效的小时延故障模拟方法

随着集成电路工艺尺寸不断缩小,电路规模不断增大,要得到很高的小时延故障覆盖率所需的测试向量越来越多,致使小时延故障模拟成本越来越高.为了降低模拟成本,提出一个高效的小时延故障模拟器.模拟方法中引入新的波形表达方式,按电路结构的拓扑顺序进行分级模拟,最后可得到每个故障的检测区间,并且应用时延故障概率分布来计算故障覆盖率.实验结果表明,此方法能大幅降低模拟时间和内存消耗.

An Efficient Fault Simulation Method for Small-delay Faults

It needs much more test patterns to get high small delay fault coverage for the shrinking circuit process technologies and increasing scale of ICs,so that the simulation cost of small delay faults becomes more and more higher.A new efficient small delay fault simulator is presented for reducing testing cost.For this method,a new waveform expression method is introduced,the circuit is simulated hierarchically in topological order and detection interval of every fault can be obtained,delay defect distribution is used to calculate the coverage.Experiments results show that this approach can decrease both simulation time and memory consumption sharply.