基于全状态伪随机序列的BIST设计

全状态伪随机序列发生器（ASPRG）是在FSR的基础上，通过修改其反馈函数而得到，其最大的优点就是利用了移位寄存器的全部状态，序列最大长度为2^n。本文首先推导得到4位和8位ASPRG的反馈网络函数，在此基础上应用ASPRG进行内建自测试（Build In Self Test）设计并优化电路结构，ASPRG既作为测试信号发生器，而它的另一种工作模式则作为特征分析使用。这样不仅简化了BIST设计，同时降低了功耗，具有较高的现实意义。

The Research and Design BIST Based All Status Pseudo-Random Sequence Generators

T he A l-l Status Pseudo-Random sequence Gener ator ( ASPRG) is based on the FSR, obtained that thro ug h modify ing it s feedback t ransfer funct io n, it s bigg est merit is that the shif t register states are all used ) ) ) the g reatest leng th is 2n . T he paper obtained 4-bit and 8-bit feedback funct ion of ASPRG by deduct ion, then carried on design the BIST using ASPRG and opt imized elect ric circuit str ucture, the ASPRG is used as the test sequence generator, but its ano ther kind of w orking pat tern w as used to characterist ic analysis. No t only simplif ied the BIST desig n, simultaneously reduced the pow er loss, and has the hig her practical sig nif icance.