Automating the addition of fault tolerance with discrete controller synthesis |
| |
Authors: | Alain Girault Éric Rutten |
| |
Affiliation: | 1.POP ART project-team and LIG laboratory,INRIA Grenoble Rh?ne-Alpes and Grenoble University,Saint-Ismier cedex,France;2.SARDES project-team and LIG laboratory,INRIA Grenoble Rh?ne-Alpes and Grenoble University,Saint-Ismier cedex,France |
| |
Abstract: | Discrete controller synthesis (DCS) is a formal approach, based on the same state-space exploration algorithms as model-checking.
Its interest lies in the ability to obtain automatically systems satisfying by construction formal properties specified a
priori. In this paper, our aim is to demonstrate the feasibility of this approach for fault tolerance. We start with a fault
intolerant program, modeled as the synchronous parallel composition of finite labeled transition systems; we specify formally
a fault hypothesis; we state some fault tolerance requirements; and we use DCS to obtain automatically a program, having the
same behavior as the initial fault intolerant one in the absence of faults, and satisfying the fault tolerance requirements
under the fault hypothesis. Our original contribution resides in the demonstration that DCS can be elegantly used to design
fault tolerant systems, with guarantees on key properties of the obtained system, such as the fault tolerance level, the satisfaction
of quantitative constraints, and so on. We show with numerous examples taken from case studies that our method can address
different kinds of failures (crash, value, or Byzantine) affecting different kinds of hardware components (processors, communication
links, actuators, or sensors). Besides, we show that our method also offers an optimality criterion very useful to synthesize
fault tolerant systems compliant to the constraints of embedded systems, like power consumption. |
| |
Keywords: | |
本文献已被 SpringerLink 等数据库收录! |
|