虚拟逻辑分析仪控制电路的设计与实现

介绍一种基于虚拟仪器技术的逻辑分析仪控制电路的设计和 Verilog HDL 的实现方 法。概述虚拟逻辑分析仪的系统总体结构和工作原理，详述控制电路的设计和部分功能模块，给 出时钟选择、触发识别与存储控制的 Verilog HDL 的设计代码，并给出了顶层模块仿真图。

The Design and Implementation of Virtual Logic Analyzer Controller

A design method of a logic analyzer controller which is based on the virtual instrument technology and the implementation using Verilog HDL is introduced.The whole construction and operational principle of the VLA are provided, the design of control circuit and some functional modules are presented in details,the Verilog HDL code of clock_select module,triggering_identify and storage_control module are given,meanwhile the simulation of the top module are given.