一种适用于非对称主从IP核的低功耗路由器结构

大规模及超大规模集成电路的快速发展使片上网络系统成为现实，同时也使十几个平方厘米芯片的功耗达到了上百瓦，而且随着集成电路规模的发展，功耗参数也在不断上升。深微亚领域的研究使得片上网络芯片的面积不断缩小，从而使得IP核互连通信中时延和能耗成为了现代片上网络系统的主要考虑因素。本丈主要分析片上网络系统的平均时延以及内部负责主要通信任务的路由器的结构，功耗，及其功耗降低的方法。

One low-power router structure for master-slave IP core NOC

The large-scale and ultra large scale integrated circuit to enable the rapid development of on-chip networks become a reality. However, it also increase the large chip＇ s power consumption to hundreds of watts. With the development of integrated circuits, power parameter is also rising. This paper mainly analyzes the average on-chip network delay as well as internal communications tasks for the main structure of the router, power, and power consumption reduction method.