| H.264 CABAC加速器的设计 |
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| 引用本文： | 杨建,刘坤杰,严晓浪,葛海通. H.264 CABAC加速器的设计[J]. 微电子学, 2007, 37(2): 265-269 |
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| 作者姓名： | 杨建 刘坤杰 严晓浪 葛海通 |
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| 作者单位： | 浙江大学,超大规模集成电路设计研究所,浙江,杭州,310027 |
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| 摘 要： | H.264主要档次采用的CABAC熵编码技术在提高视频压缩比率的同时,严重增加了编/解码的计算复杂度,嵌入式系统由于其低成本低功耗的要求,需要专用硬件加速器来进行CABAC编/解码。设计了一个高性能H.264 CABAC硬件加速器,该加速器可配置为编码或解码模式,高效地实现CABAC编/解码操作。通过性能评估实验,在220 MHz时钟频率下,该加速器能够实现平均147 Mbps(1.5 cycle/bit)的编码速度和220 Mbps(1 cycle/bit)的解码速度。与软件实现相比,加速器获得50倍以上的性能提升。
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| 关 键 词： | 视频编解码 自适应二值算术编码 加速器 |
| 文章编号： | 1004-3365（2007）02-0265-05 |
| 修稿时间： | 2006-07-202006-11-15 |
Design of an H.264 CABAC Accelerator |
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| YANG Jian,LIU Kun-jie,YAN Xiao-lang,GE Hai-tong. Design of an H.264 CABAC Accelerator[J]. Microelectronics, 2007, 37(2): 265-269 |
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| Authors: | YANG Jian LIU Kun-jie YAN Xiao-lang GE Hai-tong |
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| Affiliation: | Institute of VLSI Design, Zhejiang University, Hangzhou, Zhejiang 310027, P. R, China |
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| Abstract: | The CABAC entropy coding in the H.264 main profile improves the compression ratio at the cost of heavy computing complexity.It needs to be accelerated by hardware to satisfy the low cost and low power constraints of an embedded video system.The design of a high performance H.264 CABAC accelerator is described,which can be configured either as an encoder or a decoder.The accelerator can perform CABAC calculation efficiently.Performance evaluation shows the accelerator can achieve 147 Mbps(1.5 cycle/bit) encoding speed and 220 Mbps(1 cycle/bit) decoding speed under 220 MHz operation frequency,which is a speedup above 50 X,compared with software implementation. |
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| Keywords: | H.264/AVC |
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