基于UVM的PCI Express总线控制器验证平台

针对高速外设部件互连(Peripheral Component Interconnect Express,PCIe)总线控制器数据格式复杂、链路状态繁多的特点,提出了基于System Verilog语言的通用验证方法学(Universal Verification Methodology,UVM)验证平台。相较于传统定向验证方法,该验证平台中的验证用例使用受约束的随机方式对PCIe模块进行充分验证,能自动进行结果比对,并在回归测试中自动收集覆盖率数据。结果表明,该验证平台可以快速定位设计缺陷,在兼顾较好的可重用性和可配置性的同时,实现覆盖率验证目标,大大提高验证效率。

UVM-Based Verification Platform for PCI Express Bus Controller

For peripheral component interconnect express(PCIe)bus controller,aiming at the characteristics of complicated data format and various link state,a universal verification methodology(UVM)verification platform is built based on System Verilog.Different from traditional directional verification platform,this verification platform uses constrained random test case to verify PCIe bus controller comprehensively,and analyzes result and collects functional coverage automatically.According to the results of verification,this verification platform can efficiently find out bugs in design,fulfill coverage requirement,and improve verification efficiency with excellent configurability and reusability.