18bit 20MS/s流水线ADC架构及行为级模型设计

为了设计出满足高端仪器仪表、电子通信设备等应用需求的高速高精度模数转换器(Analog-to-Digital Converter,ADC),提出了一种精度为18 bit、采样率为20 MS/s的流水线ADC架构。使用Verilog-A语言对每一级流水级中的子模数转换电路(Sub-Analog-to-Digital Converter,Sub-ADC)、乘法数模转换电路(Multiplying Digital-to-Analog Converter,MDAC)等关键电路进行建模,进而搭建出该ADC的整体行为级模型,并基于Cadence的Spectre仿真平台进行仿真验证。在理想情况下,得到的有效位数(Effective Number of Bits,ENOB)为18.01 bit,信噪失真比(Signal to Noise and Distortion Ratio,SNDR)为110.44 dB,无杂散动态范围(Spurious Free Dynamic Range,SFDR)为122.41 dB,验证了所设计的流水线ADC的架构和行为级模型的正确性。在加入运放有限增益、电容失配等非理想因素后,该Verilog-A行为级模型也有效反映出非理想因素对电路性能的影响。将行为级模型与数字校准算法联合仿真,证明了所设计的数字算法能够有效降低非理想因素对电路性能产生的影响。

Architecture and Behavioral Model Design of 18 bit 20 MS/s Pipeline ADC

In order to design a high-speed and high-resolution analog-to-digital converter(ADC)that meets the needs of high-end instrumentation,electronic communication equipment and other applications,a pipeline ADC architecture with 18-bit resolution and 20 MS/s sampling rate is proposed.Verilog-A language is used to model key circuits such as sub-analog-to-digital converter(Sub-ADC)and multiplying digital-to-analog converter(MDAC)in each pipeline stage,and then the overall behavioral model of the ADC is built.Perform simulation verification is carried out based on Cadence's Spectre simulation platform.The effective number of bits(ENOB)is 18.01 bit,the signal to noise and distortion ratio(SNDR)is 110.44 dB,and the spurious free dynamic range(SFDR)is 122.41 dB with ideal parameters,verifying the correctness of the designed pipeline ADC architecture and behavioral model.The Verilog-A behavioral model also effectively reflects the influence of non-ideal factors on circuit performance after adding non-ideal factors such as limited gain and capacitance mismatch.By simulating the behavioral model with the digital calibration algorithm,it is proved that the digital algorithm can effectively reduce the influence of non-ideal factors on the circuit performance.