| 基于65nm工艺数字IC物理设计中信号串扰的预防 |
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| 引用本文： | 王淑芬,吴秀龙.基于65nm工艺数字IC物理设计中信号串扰的预防[J].电子技术,2012,39(1):47-48. |
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| 作者姓名： | 王淑芬 吴秀龙 |
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| 作者单位： | 安徽大学 微纳电子器件与集成电路设计省级实验室 安徽合肥 |
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| 基金项目： | 安徽省教育厅重点科研项目 |
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| 摘 要： | 数字集成电路的不断发展和制造工艺的不断进步,使得物理设计面临着越来越多的挑战.特征尺寸的减小,使得后端设计过程中解决信号完整性问题是越来越重要.互连线间的串扰就是其中的一个,所以在后端设计的流程中,对串扰的预防作用也显得尤为重要.本文就TSMC 65nm工艺下,根据具体的设计模块,探索物理设计流程中如何才能更好的预防串扰对芯片时序的影响.
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| 关 键 词： | 串扰 物理设计 数字集成电路 |
The Prevention of Signal Crosstalk in Digital IC Physical Design Based on 65nm Technology |
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| Wang Shufen
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Wu Xiulong.The Prevention of Signal Crosstalk in Digital IC Physical Design Based on 65nm Technology[J].Electronic Technology,2012,39(1):47-48. |
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| Authors: | Wang Shufen Wu Xiulong |
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| Affiliation: | (Anhui Provincial Laboratory of Micro-nano Electronic Devices and IC Design,Anhui University,Hefei,Anhui) |
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| Abstract: | With the development and the improvement of manufacturing technology of digital IC,the physical design faces more and more challenges.With the reduction of characteristic dimension,how to resolve the problem of signal integrality during back-end design becomes more important.The crosstalk between interconnection lines is one of them,so it is very important to prevent from crosstalk in the back-end design.This thesis will explore how to prevent from the influence of crosstalk on chip timing in the physical design flow based on TSMC 65nm technology and specific design module. |
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| Keywords: | crosstalk physical design digital IC |
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