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Synthesis method for testable electrical networks using 1st order building blocks |
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| Authors: | José Vicente Calvano Antônio Carneiro de Mesquita Filho Vladimir Castro Alves Marcelo Soares Lubaszewski |
| Affiliation: | a Brazilian Navy Research Institute, R. Ipiru, 2, I. do Governador, Rio de Janeiro, Brazil b Federal University of Rio de Janeiro/COPPE/PEE, Cidade Universitária, Rio de Janeiro, Brazil c Federal University of Rio Grande do Sul/DELET, Av. Oswaldo Aranha, 103, Porto Alegre, Brazil |
| Abstract: | This work presents a method for synthesizing testable continuous-time linear time-invariant electrical networks using 1st order blocks for the implementation of analog linear circuits. A functional-structural fault model for the block, and a fault dictionary are proposed together with a simple set of test vectors. The method allows, also, the fault grade evaluation for the modeled faults. The results obtained from the two application examples have shown the suitability of the approach as a design for test method for analog circuits. |
| Keywords: | Analog test Analog fault model Design for test |
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