TPC码译码器硬件仿真的优化设计

介绍一种TPC码迭代译码器的硬件设计方案,基于软判决译码规则,采用完全并行规整的译码结构,使用VHDL硬件描述语言,实现了码率为1/2的(8,4)二维乘积码迭代译码器,并特别通过硬件测试激励来实时测量所设计迭代译码器的误码率情况,提出了优化设计方案,和传统的硬件仿真方法相比大大提高了仿真效率。仿真结果证明该译码器有很大的实用性和灵活性。

Optimized design of Turbo product code decoder with hardware simulation

This paper introduces a method of hardware design for Turbo product code iterative decoder. Based on soft-decision decoding principles, a parallel regular decoding architecture is proposed, and by the VHDL language, finally, a(8,4) 2-D product code iterative decoder was implemented on a FPGA circuit. We also present a method of measuring the bit error rate (BER) performance of iterative decoder in real-time using a hardware test bench. And based on this hardware simulation model ,we present highly optimized design method, this hardware test bench runs efficiently faster than traditional simulation methods. This iterative decoder implementation in a FPGA circuit and function simulation all proved this design validity and feasibility.