QR_RLS算法的浮点脉动阵结构研究与FPGA实现

随着雷达信号处理技术的不断发展,对实时并行性和处理精度都提出了更高的要求,脉动阵结构是雷达信号处理中一种关键并行处理结构.文中介绍了一种基于QR_RLS算法的浮点脉动阵结构.为了提高运算速度,充分利用资源,引入了自定义浮点格式及该格式下的浮点运算单元的设计,并改进了平方根算法,提高了运算精度.在FPGA上实现了这种脉动阵结构,结果表明这种自定义浮点格式的脉动阵结构在提高了运算精度的同时,降低了相应的资源占用率,对实时信号处理的工程设计具有较高的参考价值.

A Study on Floating-point Systolic Array Structure and FPGA Implementation Based on QR_RLS Algorithm

With the continuous development of radar signal processing technology,more requirements for parallel processing and precision have been put forward.Systolic structure is one of the key structures of parallel processing in radar signal processing.In this paper,a floating-point systolic structure based on QR_RLS algorithm is described.To improve computing speed and take advantage of multiplier resources,a custom floating-point format and the floating-point unit design in the format are introduced.Also,the squ...